000000224 001__ 224
000000224 005__ 20231130114543.0
000000224 0247_ $$2DOI$$a10.6083/M41V5BXW
000000224 037__ $$aETD
000000224 245__ $$aBit-sliced design of a graph reduction processor
000000224 260__ $$bOregon Graduate Center
000000224 269__ $$a1986
000000224 336__ $$aThesis
000000224 502__ $$bM.S.
000000224 540__ $$fCC BY
000000224 542__ $$fIn copyright - single owner
000000224 6531_ $$agraph grammars
000000224 6531_ $$afunctional programming (computer science)
000000224 6531_ $$acomputer architecture
000000224 692__ $$aDepartment of Computer Science and Engineering$$041405
000000224 7001_ $$aVireday, Richard P.
000000224 7001_ $$uOregon Graduate Center$$041351
000000224 8564_ $$9125d1e67-0a58-4474-ab5a-61a1855b0c60$$s4223370$$uhttps://digitalcollections.ohsu.edu/record/224/files/224_etd.pdf
000000224 905__ $$a/rest/prod/34/84/zg/92/3484zg926
000000224 909CO $$ooai:digitalcollections.ohsu.edu:224$$pstudent-work
000000224 980__ $$aTheses and Dissertations