@article{ETD,
      recid = {2288},
      author = {Torres Robles, Juan},
      title = {Integrated circuit layout design methodology for deep  sub-wavelength processes},
      publisher = {Oregon Health and Sciences University},
      school = {Ph.D.},
      address = {2005-07-01},
      number = {ETD},
      abstract = {One of  the  critical aspects of semiconductor fabrication   is the  patterning  of  multiple  design  layers  onto  silicon  wafers.  Since  180nm  processes came  online,   the  semiconductor  industry  has  operated  under  conditions in  which the critical features are smaller than  the wavelength of light used during the patterning process.   Such  sub-wavelength  conditions  present  many challenges   because topology,  rather than  feature width and space,  defines the yield characteristics of the devices.},
      url = {http://digitalcollections.ohsu.edu/record/2288},
      doi = {https://doi.org/10.6083/M42J6956},
}