TY  - GEN
AB  - One of  the  critical aspects of semiconductor fabrication  is the  patterning  of  multiple  design  layers  onto silicon  wafers.  Since  180nm  processes came  online,  the  semiconductor  industry  has  operated  under conditions in  which the critical features are smaller than the wavelength of light used during the patterning process.  Such  sub-wavelength  conditions  present  many challenges  because topology,  rather than  feature width and space, defines the yield characteristics of the devices.
AD  - Oregon Health and Science University
AU  - Torres Robles, Juan
DA  - 2005-07-01
DO  - 10.6083/M42J6956
DO  - DOI
ED  - Berglund, Neil
ED  - Advisor
ID  - 2288
L1  - https://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf
L2  - https://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf
L4  - https://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf
LK  - https://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf
N2  - One of  the  critical aspects of semiconductor fabrication  is the  patterning  of  multiple  design  layers  onto silicon  wafers.  Since  180nm  processes came  online,  the  semiconductor  industry  has  operated  under conditions in  which the critical features are smaller than the wavelength of light used during the patterning process.  Such  sub-wavelength  conditions  present  many challenges  because topology,  rather than  feature width and space, defines the yield characteristics of the devices.
PB  - Oregon Health and Sciences University
PY  - 2005-07-01
T1  - Integrated circuit layout design methodology for deep sub-wavelength processes
TI  - Integrated circuit layout design methodology for deep sub-wavelength processes
UR  - https://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf
Y1  - 2005-07-01
ER  -