000002288 001__ 2288 000002288 005__ 20250313103752.0 000002288 0247_ $$2DOI$$a10.6083/M42J6956 000002288 037__ $$aETD 000002288 245__ $$aIntegrated circuit layout design methodology for deep sub-wavelength processes 000002288 260__ $$bOregon Health and Sciences University 000002288 269__ $$a2005-07-01 000002288 336__ $$aDissertation 000002288 502__ $$bPh.D. 000002288 502__ $$gComputer Science & Electrical Engineering (sunsetting) 000002288 520__ $$aOne of the critical aspects of semiconductor fabrication is the patterning of multiple design layers onto silicon wafers. Since 180nm processes came online, the semiconductor industry has operated under conditions in which the critical features are smaller than the wavelength of light used during the patterning process. Such sub-wavelength conditions present many challenges because topology, rather than feature width and space, defines the yield characteristics of the devices. 000002288 542__ $$fIn copyright - single owner 000002288 691__ $$aOGI School of Science and Engineering$$041365 000002288 7001_ $$aTorres Robles, Juan$$uOregon Health and Science University$$041354 000002288 7201_ $$aBerglund, Neil$$uOregon Health and Science University$$041354$$7Personal$$eAdvisor 000002288 8564_ $$9e72571e0-c700-4b87-ad8a-15483545e138$$s14839510$$uhttps://digitalcollections.ohsu.edu/record/2288/files/3018_etd.pdf 000002288 905__ $$a/rest/prod/kw/52/j8/18/kw52j8181 000002288 909CO $$ooai:digitalcollections.ohsu.edu:2288$$pstudent-work 000002288 980__ $$aTheses and Dissertations