000007917 001__ 7917
000007917 005__ 20250430112605.0
000007917 0247_ $$2DOI$$a10.6083/M4765CN1
000007917 037__ $$aETD
000007917 245__ $$aComparison of CMOS XOR and XNOR gate design
000007917 260__ $$bOregon Health and Science University
000007917 269__ $$a2002-08-01
000007917 336__ $$aThesis
000007917 502__ $$bM.S.
000007917 520__ $$aTwo  new  methods  are  proposed  to  implement  the exclusive-OR and exclusive-NOR functions  at  the  transistor  level. The first  method  uses  non-complementary  signal input  and the least  number of  transistors.  The second method  improves the performance but  two additional  transistors are utilized.  The proposed  method uses  the same number of transistors  but  adds  with  more  drive  capability. These  circuits  were  first  implemented using  a Physical Layout  Design  tool  produced  by  Mentor Graphics.  These layouts  were extracted  and  simulated  using  circuit  simulator  HSPICE  and  ACCUSIM. Delay  and power  consumption  of  these  circuits  were  characterized  and  compared  with  previously  known  designs.
000007917 540__ $$fCC BY
000007917 542__ $$fIn copyright - single owner
000007917 650__ $$aElectronics$$018298
000007917 650__ $$aSignal Processing, Computer-Assisted$$025995
000007917 6531_ $$aelectronic circuits
000007917 691__ $$aOGI School of Science and Engineering$$041365
000007917 692__ $$aOGI Department of Electrical and Computer Engineering$$041409
000007917 7001_ $$aTang, Makara$$uOregon Health and Science University$$041354
000007917 7201_ $$aLu, Shih-Lien$$uIntel Corporation$$7Personal$$eAdvisor
000007917 8564_ $$922ad8659-e09d-4dea-9330-201e78741589$$s4614028$$uhttps://digitalcollections.ohsu.edu/record/7917/files/200208.tang.makara.pdf$$ePublic$$2fc19a5c1373d03916f5c60553d1abce2$$31
000007917 905__ $$a/rest/prod/3n/20/3z/71/3n203z71w
000007917 909CO $$ooai:digitalcollections.ohsu.edu:7917$$pstudent-work
000007917 980__ $$aTheses and Dissertations