For the trend of IC device speed to keep increasing while their physical dimension decreases, new materials will have to be adopted into their fabrication. Some new materials are the replacement of the interlayer dielectric (ILD) with an ultra-low-k material (k < 2.2) and the use of copper (Cu) for interconnects. In modern IC integration the Cullow-k scheme is widely accepted, and to remove the unwanted Cu the damascene process is the traditional method throughout the IC industry. Chemical mechanical planarization (CMP) is the process of choice for the damascene method, but unfortunately, it damages the fragile ultra-low-k dielectric. In this research, the investigation of electro-polishing (EP) was studied to determine if it can be used to replace the CMP process.