Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits

As nanoscale electronics become increasingly unreliable, interest has grown in fault‑tolerant (FT) logic design, which enables reliable systems to be built from unreliable components. At the same time, rising wire delays and the high power cost of clock distribution in deep‑submicron technologies have renewed attention to asynchronous, or clockless, circuit design. This dissertation explores the use of triple modular redundancy (TMR), a classical FT approach, to enhance the reliability of asynchronous systems. A new fault model tailored to clockless circuits is developed and applied to both nonredundant and triplex micropipelines. Additionally, a combined Muller C‑element and majority gate is introduced to address interface issues between simplex and triplex domains. Monte Carlo simulations of representative Verilog‑modeled circuits demonstrate the effectiveness of TMR‑based strategies for improving reliability in asynchronous nanoelectronic designs.