Packet classification is a fundamental function performed by networking devices such as routers, switches, and firewalls. Approaches for designing packet classification algorithms are typically based on the hardware they are run on. Programmable network processors are an emerging platform that aims to offer the flexibility of software while achieving performance comparable to custom hardware. A key architectural feature of typical network processors is that the hardware is highly optimized to provide parallel execution of code. This thesis studies how different design approaches of mapping a parallel-search packet classification algorithm onto a network processor may affect its performance/packet-processing speed.